The present invention relates to the biasing of a differential stage with active load, e.g., a transconductor. More particularly, the present invention relates to a precision biasing circuit in which the biasing circuit and the main circuit have almost identical biasing conditions.
The transconductance of a differential stage is controlled by its tail current. The tail current is in turn obtained by mirroring a reference current. In certain applications like controlled amplifiers or continuous-time filters that use transconductors, the reference current is used to adjust some of the characteristics of the transconductor (e.g. the transconductance). The accuracy of the replication of the reference current directly affects the performance of the transconductor, and so it is desirable to provide a circuit that very accurately replicates a reference current.
It would also be desirable to accurately mirror the reference current, especially for a low supply voltage.
Some applications, like programmable gain amplifiers, require a transconductor to be switched onto and off of a low input impedance stage, such as a cascode or a folded-cascode. In the latter case, the folded-cascode generally has a fully differential configuration and has its bias set by an output common-mode control loop. If there is a net DC output current from the transconductor, the common-mode control loop has to adjust the bias of the output stage every time the configuration changes by switching ON or OFF transconductors.
It would also be desirable to be able to accurately bias the active load of a differential stage in order to reduce the DC output currents of the differential stage connected to a folded-cascode current to be substantially zero.
FIG. 1 shows a conventional circuit 100 for biasing a differential stage. The circuit includes a differential stage 105, a lower current mirror 110, an upper current mirror 120, a bias current source 125, and first and second voltage sources 130 and 135, representing the equivalent circuits of low impedance loads, e.g., as seen in FIG. 5 below.
The differential stage 105 includes first through fourth differential transistors TD1, TD2, TD3, and TD4. The lower current mirror 110 includes first and second mirror transistors TM1 and TM2. The upper current mirror 120 includes a third mirror transistor TM3 and the third and fourth differential transistors TD3 and TD4. The input transistors TD1 and TD2 are driven with respect to the common mode voltage VCOM by the voltages vid/2 and xe2x88x92vid/2, respectively.
A tail current IT is obtained by mirroring a reference current IBIAS through the first and second mirror transistors TM1 and TM2. Under ideal conditions, the tail current can be calculated as follows.
IT=2nxc2x7IBIASxe2x80x83xe2x80x83(1)
where n is determined by the ratio of the geometric features of first and second mirror transistors TM1 and TM2 as follows.                     n        =                              1            2                    ·                                    (                                                W                  M1                                                  L                  M1                                            )                                      (                                                W                  M2                                                  L                  M2                                            )                                                          (        2        )            
where WM1 is the width of the first mirror transistor, LM1 is the length of the first mirror transistor, WM2 is the width of the second mirror transistor, and LM2 is the length of the second mirror transistor.
The accuracy of the mirroring is affected by the usually different drain-source voltages of the first and second mirror transistors TM1 and TM2.
One way to improve the current mirroring is to use cascode current mirrors, as shown in FIG. 2. The circuit of FIG. 2 includes a differential stage 105, a cascode current mirror 210, a bias current generator 125, and first and second voltage sources 130 and 135. The cascode current mirror 210 includes fourth, fifth, sixth, and seventh mirror transistors TM4, TM5, TM6, and TM7.
However, the cascode current mirrors have minimum voltage requirements that in many low-voltage deep-submicron circuits cannot be accommodated. As a result, the voltage at the node B must meet the following equality:
VBmin=2xc2x7xcex94V+VTHxe2x80x83xe2x80x83(3)
where VTH is the threshold voltage of the fourth, fifth, sixth, and seventh mirror transistors TM4, TM5, TM6, and TM7, and                               Δ          ⁢                      xe2x80x83                    ⁢          V                =                                            I              T                                      K              ⁡                              (                                                      W                    M6                                                        L                    M6                                                  )                                                                        (        4        )            
where IT is the tail current, WM6 is the width of the sixth mirror transistor TM6, LM6 is the length of the sixth mirror transistor TM6, and K is a process-dependent parameter calculated as follows.                     K        =                              μ            ·                          C              ox                                2                                    (        5        )            
where xcexc is the average mobility of the majority carriers in the channel, and Cox is the specific capacitance of the gate oxide.
For these equations, it is assumed that all of the bias transistors in one chain (TM5 and TM7, TM4 and TM6) are identical, and the body effect is neglected. Unfortunately, the minimum voltage on the B node VBmin limits the input voltage range of the differential pair formed by the first and second differential transistors TD1 and TD2.
A circuit using for bias a high swing cascode is shown in FIG. 3. The circuit of FIG. 3 includes a differential stage 105, a high swing cascode current mirror 310, first and second bias current sources 323 and 327, and first and second voltage sources 130 and 135. The high swing cascode current mirror 310 includes eighth through twelfth mirror transistors TM8 to TM12.
The first and second bias current sources 323 and 327 do not necessarily supply the same current. Their output currents depend upon the relative sizes of the transistors TM10, TM11, and TM12.
The circuit shown in FIG. 3 acts to lessen the minimum voltage at the node B to:
VBmin=2xc2x7xcex94Vxe2x80x83xe2x80x83(5)
Unfortunately, this may still not be low enough for certain bias conditions. In fact, many circuits require constant transconductance over process, temperature and power supply variations, which can easily cause a need for a 2:1 change in the bias current.
In each of the designs disclosed in FIGS. 1 to 3, the third and fourth differential transistors TD3 and TD4 of the differential pair 105 act as fixed current sources. In addition, the differential pair 105 itself also acts as a controlled current source. The output current of each branch of the differential stage TD15, TD2, TD3, and TD4 is injected into an ideally zero input impedance stage, i.e., the first and second voltage sources 130 and 135.
FIG. 4 shows and alternate configuration in which a transconductor is followed by a folded-cascode stage. The circuit of FIG. 4 includes a differential stage 405 (voltage-to-current converter), a current mirror 110, a bias current source 125, and a folded-cascode 450. The folded-cascode 450 includes first through fourth folded-cascode transistors TFC1 to TFC4, a voltage amplifier 460, and first and second load current sources 470 and 475, and provides first and second output currents IO1 and IO2. The differential stage 405 includes first and second differential transistors TD1 and TD2.
In the circuit of FIG. 4, the loads of the differential stage are merged with the current sources of the folded-cascode and appear as the third and fourth folded-cascode transistors TFC3 and TFC4. Their currents are controlled by a common-mode feedback loop including the first and second transistors TFC1 and TFC2, and the voltage amplifier 460.
FIG. 5 shows a folded-cascode transconductor that employs a separate input stage and folded-cascode for an NMOS differential stage. The circuit of FIG. 5 includes a differential stage 105, a lower current mirror 110, an upper current mirror 120, a bias current source 125, and a folded-cascode 450. The differential stage 105 provides first and second DC output currents IDCO1 and IDCO2 to the folded-cascode 450.
A circuit similar to that of FIG. 5 is shown, for example, in J- E. Kardontchik, Introduction to the Design of Transconductor-Capacitor Filters, Kluwer International Series in Engineering and Computer Sciences, 1992, which is incorporated by reference in its entirety. The purpose of this design is to have zero DC output currents IDCO1 and IDCO2 from the differential amplifier 105.
However, because of the different drain-source voltage of the transistors in the upper current mirror 120 (i.e., TD3, TD4, and TM1), first and second currents ID3 and ID4 flowing through the third and fourth differential transistors TD3 and TD4 will be different from the ideally mirrored bias current nxc2x7IBIAS. As a result, because of the imperfections affecting both the upper current mirror 120 and the lower current mirror 110, there are net DC output currents IDCO1 and IDCO2 flowing out of the differential stage 105. In this case, xe2x80x98nxe2x80x99 is the value determined by equation (2).
In other words, under ideal circumstances,
IT=(ID3+ID4)=(ID1+ID2)xe2x80x83xe2x80x83(7)
However, because the current mirrors 110 and 120 are imperfect, this equality is not correct. As a result, (ID3xe2x89xa0ID1) and (ID4xe2x89xa0ID2), which makes the DC output currents IDCO1 and IDCO2 non-zero.
FIG. 6 is a circuit diagram of a conventional two-input stage differential output folded-cascode with separated loads for the input stages. The circuit of FIG. 6 includes primary and secondary differential stages 605a and 605b, a lower current mirror 610, an upper current mirror 620, a bias current source 125, and a folded-cascode 450. As shown in FIG. 6, this circuit uses multiple differential stages 605a and 605b in association with a single folded-cascode 450.
The primary differential stage 605a includes first through fourth primary transistors TD1A, TD2A, TD3A, and TD4A. The primary differential stage 605a provides first and second DC output currents IDCO1 and IDCO2 to the folded-cascode 450. The secondary differential stage 605b includes first through fourth secondary transistors TD1B, TD2B, TD3B, and TD4B. The secondary differential stage 605b provides third and fourth DC output currents IDCO3 and IDCO4 to the folded-cascode 450.
The lower current mirror 610 includes thirteenth through fifteenth mirror transistors TM13 to TM15. The upper current mirror 620 includes a sixteenth mirror transistor TM16, the third and fourth current source transistors TD3A and TD4A, and the third and fourth current source transistors TD3B and TD4B.
FIG. 7 is a circuit diagram of a conventional switched input stages differential output folded-cascode with separated loads for the input stages. The circuit of FIG. 7 includes primary and secondary differential stages 605a and 605b, a lower current mirror 610, an upper current mirror 620, a bias current source 125, a folded-cascode 450, and first through fourth MOS switches S1 to S4.
As shown in FIG. 7, the transconductors, i.e., the differential stages 605a and 605b, in this circuit must be switched on and off of the folded-cascode 450. In this design, the differential stages 605a and 605b are connected to the folded-cascode 450 through the switches S1, S2, S3, and S4. In particular, the primary differential stage 605a is connected to the folded-cascode 450 through the first and second switches S1 and S2, and the secondary differential stage 605b is connected to the folded-cascode 450 through the third and fourth switches S3 and S4.
Because of the imperfections in the upper and lower current mirrors 610 and 620, there are net DC output currents IDCO1, IDCO2, IDCO3, and IDCO4 flowing out of the primary and secondary differential stages 605a and 605b. When the input stages are switched on or off, these non-zero DC output currents will force the output stage, i.e., the folded-cascode 450, to adjust its operating point through a common-mode feedback. Unfortunately, the changing of the operating point of the output stage can be detrimental to its performance, and should be avoided, if possible.
It would therefore be desirable to provide a precision bias for a transconductor in which the bias circuit and the main circuit have substantially identical operating conditions.
It is thus an object of the present invention to provide a precision biasing circuit that can accurately provide for the biasing of a differential stage having an active load. It is also an object of the present invention to accurately reflect a bias current into the differential stage.
In an effort to meet these and other objects of the invention, and according to one aspect of the present invention, a precision bias for a differential transconductor is provided. The precision bias comprises: a bias circuit for providing a bias current; a differential amplifier for receiving a tail current; and a first mirror transistor for receiving the bias current from the bias circuit; a second mirror transistor, connected to the first mirror transistor in a current mirror configuration, for providing the tail current to the differential amplifier. The drain-to-source voltages of the first and second mirror transistors are preferably substantially the same.
The bias circuit may comprise a bias current source for providing the bias current; and a bias transistor formed between the bias current source and the first mirror transistor, the bias transistor operating to supply the same drain-to-source voltage to the first mirror transistor that the differential amplifier supplies to the second mirror transistor. The drain of the bias transistor may be connected to the gates of the first and second mirror transistors. The differential amplifier may comprise first and second differential transistors connected as a differential pair. The gate of the bias transistor may be connected to a voltage equal to the input common mode voltage of the differential amplifier, wherein                     W        D1                    L        D1              =                            W          D2                          L          D2                    =              n        ·                              W            B                                L            B                                ,
and wherein                     W        M2                    L        M2              =          2      ⁢              n        ·                              W            M1                                L            M1                                ,
where WD1 and LD1, and WD2 and LD2, are the widths and lengths of the first and second differential transistors, respectively, WM1 and LM1, and WM2 and LM2, are the widths and lengths of the first and second mirror transistors, respectively, WB and LB are the width and length of the bias transistor, and n is an positive number. The bias circuit may further comprise a non-inverting amplifier connected between the drain of the bias transistor and the gates of the first and second mirror transistors.
The differential amplifier may comprise: first and second differential transistors, each having a source terminal connected to a drain of the second mirror transistor; a third differential transistor having a drain connected to the drain of the first differential amplifier, acting as a first load; and a fourth differential transistor having a drain connected to the drain of the second differential amplifier, acting as a second load. The current of the third differential transistor preferably substantially matches the current of the first differential transistor, and the current of the fourth differential transistor preferably substantially matches the current of the second differential transistor.
Also to achieve the goals of the current invention, there is provided a precision bias for a differential transconductor that comprises: a bias transistor for providing a bias current, having a gate connected to a common voltage and a drain connected to a first reference node; a first level-setting amplifier connected between a supply voltage and ground, having a first control voltage from the first reference node as input, and a first level-setting voltage as output; an inverting amplifier for generating a first current setting voltage by inverting, amplifying, and level shifting the first level setting voltage; a first current generator connected to the supply voltage, for receiving the first current setting voltage as an input, for generating a tail current, and for generating the bias current at a source of the bias transistor; a second current generator connected to ground, for receiving a bias voltage as a second current generator input, and for generating the bias current to be injected into the first reference node, and for generating first and second load currents equal to half the tail current to the second and third reference nodes, respectively; a differential stage for receiving the tail current from the first current generator, and supplying the first and second load currents to the second and third loads, respectively; a second level-setting amplifier connected between the supply voltage and ground, having a second control voltage as input, and a second level-setting voltage as output; a third level-setting amplifier connected between the supply voltage and ground, having a third control voltage as input, and a third level-setting voltage as output; a folded cascode connected between the supply voltage and ground for receiving the second and third level-setting voltages, a second current from the second node, and a third current from the third node as inputs, and for providing the second and third control voltages and first and second output currents as outputs, wherein the first, second, and third control voltages are the same.
The first level-setting amplifier may comprise a first level-setting current source and a first level-setting transistor connected in series; a gate of the first level-setting transistor may receive the first control voltage; and a first output node between the first level-setting current source and the first level-setting transistor may provide the first level-setting voltage. The second level-setting amplifier comprises a second level-setting current source and a second level-setting transistor connected in series. A gate of the second level-setting transistor preferably receives the second control voltage, and a second output node between the second level-setting current source and the second level-setting transistor preferably provides the second level-setting voltage.
The third level-setting amplifier preferably comprises a third level-setting current source and a third level-setting transistor connected in series, where a gate of the third level-setting transistor receives the third control voltage, and a third output node between the third level-setting current source and the third level-setting transistor provides the third level-setting voltage.
The first current generator preferably comprises first and second current generation transistors, the first current generation transistor providing the bias current and the second current generation transistor providing the tail current. Preferably, the following equalities are true:                     W        D1                    L        D1              =                            W          D2                          L          D2                    =              n        ·                              W            B                                L            B                                ,            and      ⁢              xe2x80x83            ⁢                        W          CG2                          L          CG2                      =          2      ⁢              n        ·                              W            GCG1                                L            CG1                                ,
where WD1 and LD1, and WD2 and LD2, are the widths and lengths of the first and second differential transistors, respectively, WCG1 and LCG1, and WCG2 and LCG2, are the widths and lengths of the first and second current generation transistors, respectively, WB and LB are the width and length of the bias transistor, and n is an positive number.
The second current generator preferably comprises third, fourth, and fifth current generation transistors. Among these current generator transistors, the following equality is preferably true:             W      CG3              L      CG3        =                    W        CG4                    L        CG4              =          n      ·                                    W            CG5                                L            CG5                          .            
The differential stage preferably comprises first and second differential transistors, where the first and second differential transistors receive the tail current at their respective sources, the first differential transistor has its drain connected to the second reference node, the second differential transistor has its drain connected to the third reference node, the first and second differential transistors are driven with respect to the common voltage by first and second differential voltages, respectively, and the first and second differential voltages are substantially identical in magnitude, but opposite in polarity.
To further achieve the goals of the present invention, another precision bias for a differential transconductor is provided. This precision bias comprises: a first bias transistor for providing a first bias current, having a first gate connected to a common voltage and a first drain connected to a first reference node; a first level-setting amplifier connected between a supply voltage and ground, having a first control voltage from the first reference node as input, and a first level-setting voltage as output; a first inverting amplifier for generating a first current setting voltage by inverting, amplifying, and level shifting the first level setting voltage; a first current generator connected to the supply voltage, for receiving the first current setting voltage as an input, for generating a tail current, for generating the first bias current at a source of the first bias transistor, and for generating a second bias current at a source of the second bias transistor; a second bias transistor for receiving the second bias current, having a second gate connected to a common voltage and a second drain connected to a second reference node; a second level-setting amplifier connected between the supply voltage and ground, having a second control voltage from the second reference node as input, and a second level-setting voltage as output; a second inverting amplifier for generating a second current setting voltage by inverting, amplifying, and level shifting the second level setting voltage; a second current generator connected to ground, for receiving the second current setting voltage as a second current generator input, and for generating the second bias current to be injected into the second reference node, and for generating first and second load currents equal to half the tail current to third and fourth reference nodes, respectively; a differential stage for receiving the tail current from the first current generator, and supplying the first and second load currents to the second and third loads, respectively; a third level-setting amplifier connected between the supply voltage and ground, having a third control voltage as input, and a third level-setting voltage as output; a fourth level-setting amplifier connected between the supply voltage and ground, having a fourth control voltage as input, and a fourth level-setting voltage as output; and a folded cascode connected between the supply voltage and ground for receiving the third and fourth level-setting voltages, a third current from the third node, and a fourth current from the fourth node as inputs, and for providing the third and fourth control voltages and first and second output currents as outputs. The first, second, third, and fourth control voltages are preferably the same.
The first level-setting amplifier preferably comprises a first level-setting current source and a first level-setting transistor connected in series, where a gate of the first level-setting transistor receives the first control voltage, and a first output node between the first level-setting current source and the first level-setting transistor provides the first level-setting voltage.
The second level-setting amplifier preferably comprises a second level-setting current source and a second level-setting transistor connected in series, where a gate of the second level-setting transistor receives the second control voltage, and a second output node between the second level-setting current source and the second level-setting transistor provides the second level-setting voltage.
The third level-setting amplifier comprises a third level-setting current source and a third level-setting transistor connected in series, where a gate of the third level-setting transistor receives the third control voltage, and a third output node between the third level-setting current source and the third level-setting transistor provides the third level-setting voltage.
The fourth level-setting amplifier comprises a fourth level-setting current source and a fourth level-setting transistor connected in series, where a gate of the fourth level-setting transistor receives the fourth control voltage, and a fourth output node between the fourth level-setting current source and the fourth level-setting transistor provides the fourth level-setting voltage.
The first current generator preferably comprises first, second, and third current generation transistors, the first current generation transistor providing the first bias current, the second current generation transistor providing the second bias current, and the third current generation transistor providing the tail current.
In the first current generator, the following equalities are preferably true:                     W        D1                    L        D1              =                            W          D2                          L          D2                    =              n        ·                              W            B                                L            B                                ,            and      ⁢              xe2x80x83            ⁢                        W          CG3                          L          CG3                      =                  2        ⁢                  n          ·                                    W              CG1                                      L              CG1                                          =              2        ⁢                  n          ·                                    W              CG2                                      L              CG2                                            ,
where WD1 and LD1, and WD2 and LD2, are the widths and lengths of the first and third differential transistors, respectively, WCG1 and LCG1, WCG2 and and LCG2, and WCG3 and LCG3, are the widths and lengths of the first, second, and third current generation transistors, respectively, WB and LB are the width and length of the bias transistor, and n is an positive number.
The second current generator comprises fourth, fifth, and sixth current generation transistors. In the second current generator, the following equality is preferably true:             W      CG4              L      CG4        =                    W        CG5                    L        CG5              =          n      ·                                    W            CG6                                L            CG6                          .            
The differential stage comprises first and second differential transistors, where the first and second differential transistors receive the tail current at their respective sources, the first differential transistor has its drain connected to the second reference node, the second differential transistor has its drain connected to the third reference node, the first and second differential transistors are driven with respect to the common voltage by first and second differential voltages, respectively, and the first and second differential voltages are substantially identical in magnitude, but opposite in polarity.